Photonic sequential logic circuits for stateful intelligence

However, constructing a Turing-complete optical computing for next-generation AI paradigms, from large language models (LLMs) to real-time autonomous systems, requires not only stateless function mapping units, but also sequential logic circuits capable of storing historical states and processing dynamic data streams.

Current photonic processors lack this temporal memory, and the state-of-the-art optical sequential schemes remain impractical due to signal attenuation and the absence of programmable clock control. Here, we propose a photonic sequential logic circuits (PSLC) to resolve this fundamental challenge. Leveraging a uniquely designed active optoelectronic feedback network, we construct a complete family of photonic sequential logic devices, comprehensively encompassing set-reset latches, D latches, and edge-triggered master-slave D flip-flops.