PVT and Monte Carlo simulation results for reference circuits developed for SiC Gate Driver IC

This dataset was built using Cadence Virtuoso after parasitic extraction of each circuit, measuring their thermal coefficient, line regulation, PSRR, gain and phase margins (only for bandgap voltage circuit). Regarding PVT simulations, there were run the following corners: - Process: typical, worst speed, worst power, worst zero, worst one. - Voltage: 4.5 V, 5 V, 5.5 V. - Temperature: -40°C, 27°C, 125°C. With respect to Monte Carlo simulation, there were performed 1000 runs under nominal conditions and process spread of 3 sigma.