Spaceborne Solid State Recorder Designed For High-speed Space Detection Missions

The core components of this architecture include a data multiplexing unit, an array of error-correcting codes (ECC) utilizing the RS(256,252) algorithm, DDR3 high-speed cache, and a flash memory control unit. Noteworthy innovations feature a nine-stage pipeline for ECC processing with the RS(256,252) algorithm and advanced storage techniques for the flash memory control unit, including interleaved storage, multi-plane operations, and caching techniques.

Additionally, the design incorporates a more optimized clock domain configuration. The SSR is designed to boost data throughput and error correction capabilities while maintaining reliable operation in the extreme conditions of outer space. System performance was evaluated using the K7 FPGA model, with a focus on throughput efficiency and stability.