A Tile-Based Multi-Core Hardware Architecture for Image Lossless Compression and Decompression

To enhance processing efficiency, the algorithm is implemented on a FPGA, with a multi-core system architecture introduced to accelerate both compression and decompression processes. The multi-core system is divided between the Processing System (PS) and Programmable Logic (PL) components, wherein the PS assists the PL in executing the compression and decompression algorithms.

The multi-core modules on the PL side are capable of processing up to eight image tiles concurrently. The compression algorithm utilizes a four-stage pipeline, while the decompression process is controlled by an efficient dynamic state machine. The coordinated operation of the PS and PL, combined with the parallel processing architecture on the PL side, significantly increases the throughput of the algorithm.