Data and code for: Characterization of a low-power 3D photon-to-digital converter readout improved for system integration in meter-scale applications

Data and code to reproduce the figures in the article "Characterization of an improved general-purpose low-power 3D photon-to-digital converter readout—toward meter-scale integration applications": Digital silicon photomultipliers (dSiPM) are arrays of single photon avalanche diodes (SPAD) where each SPAD has its own electronic readout. To maximize the photodetection area, we developed a readout integrated circuit (ROIC) 3D-integrated to a custom-designed SPAD layer fabricated at Teledyne Dalsa (Bromont, Canada) to form a photon-to-digital converter (PDC).

This paper presents an improved version of a previously demonstrated ROIC, fabricated in TSMC 180 nm technology to manage a 64 × 64 pixel architecture. Improvements lead to a reduction of the timing jitter on the flag output from 72 ps RMS to 22.6 ps RMS through optimized H-tree design, enabling sub-30 ps precision. A tunable hold-off circuit provides adjustable dead time from 32 ns to 18 μs, enabling afterpulsing mitigation to be optimized across varying operating conditions, including at cryogenic temperature.