Study of Single Event Latch-up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

The proposed method increases the range of the resistance through the wide voltage tolerance of the converter. The resistor boundary range is investigated that meets the normal operating requirement of the device while allowing the device to exit the latch-up. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance range by 300% to 400% compared to the conventional method.

And it is also demonstrated that the proposed method reduces latch-up currents to 72.1 mA and 24.2 mA at resistors of 34 Ω and 51 Ω respectively, allowing the devices to exit the latch-up.