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Data · dataset · 2026

Electrical testing of high-resistance silicon substrate MOS arrays

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A MOS array was fabricated on a 130nm 3k Ω· cm high resistance silicon substrate, and the leakage current characteristics, output curves, and transfer curves of NMOS and PMOS were tested under high substrate negative bias, respectively, as a preliminary study for MAPS chips. 

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ScienceDB10.57760/sciencedb.j00186.0078012 d agoJSON v1
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