Effective incorporation of FPGA based processing in server architectures

Whilst FPGA device sizes have increased and associated design tools have matured, there are still challenges for their seamless integration model. This acts to hamper the abstraction of FPGA as a scalable, run-time programmable and high throughput resource, which can be designed from a high-level programming environment. <br><br>This work contributes to the programming challenges in two domains; namely design process and the run-time programming.

Firstly, it builds an integration stack that enables just-in-time compilation and runtime programmability for soft-cores in data centre environments, particularly for highly dynamic task queues. It enables remote access to an independent scalable FPGA accelerator in a similar manner to software-based systems whilst providing up to 10.7× greater energy efficiency. <br><br>The work then proposes an abstracted platform-independent optimisation approach based on OpenCL for improving FPGA-based performance.