Input-aware heuristic with high-level synthesis of approximate hardware

The data were produced using an approach that maps accelerator operators, such as adders and multipliers, to a library of precharacterized approximate components in order to reduce hardware resource utilization while controlling output errors. Applications were executed with representative training inputs, and candidate approximate designs were selected using a combined metric of output error and estimated resource usage.

The dataset includes results for image processing and CNN workloads, showing that the approach can reduce LUT and FF usage by up to 55% for less than 25% output degradation, and achieve similar savings for a CNN model with less than 0.8% accuracy degradation. The repository contains application source code, configuration files, datasets, Jupyter notebooks, and component characterization data. For each application, the corresponding folder includes setup files, training and testing datasets, error evaluation scripts, hardware source code templates for Vitis, and a CSV file with component features related to error and LUT+FF utilization.